ISRO Scientist or Engineer Electronics 2018

A system generates data at a rate of 5 Mbps. In order to provide resistance to bit errors, a rate $$\frac{1}{2}$$ error correcting code is applied. Further, the data is mapped to a 16-QAM constellation. Whatis the resulting symbol rate?

Consider a binary linear code with parity check matrix H given below.
$$H = \begin{bmatrix}0 & 1 & 1 & 1 & 0 & 0 \\1 & 0 & 1 & 0 & 1 & 0 \\1 & 1 & 0 & 0 & 0 & 1 \end{bmatrix}$$
Which of the following is a valid codeword?

The minimum distance of a (n,k) = (7,4) linear block code is upper bounded by:

Consider a 4-PSK constellation with points $$\left\{\sqrt{2}, j\sqrt{2}, -\sqrt{2}, -j\sqrt{2}\right\}$$ and a 4-PAM constellation {-3, -1, 1, 3}. If all the points in the constellation occur with equal probability, the ratio of average energy of 4-PAM signal to that of 4-PSK signal is:

Difference in number of complex multiplier required for 16 point DFT and 16-point radix-2 FFT is

No of stages(S) in direct form FIR filter is given as
S = integer (K * Fs/ $$\triangle$$ f)
Where Fs = Sampling Frequency, $$\triangle$$f = Filter transition band, K = 3(assume)
If x(n) is signal with frequency range 0-2.4 MHz and sampled at $$F_s = 400$$ MHz and it is filtered by

Assumptions:
Passband Frequency LPF(1): 1.8 MHz, Stop band Frequency LPF(1) : 4 MHz
Passband Frequency LPF(2): 1.8 MHz ,Stopband Frequency LPF(2) : 2 MHz
Both filters are having flat passbands and stopbands
Passband attenuation of both filters = 0 dB and stop bandattenuation of both filters is infinity.
Calculate total no. of stages $$S_{LPF1} + S_{LPF2}$$

Difference in dynamic range of 32-bit binary number(B) and floating point number(F) is?
Standard Format for B and F as given below :

If Sys clock frequency is > 4 * clk_ext frequency. What is the functionality of above circuit?

Simplify the Boolean expression:
$$F(w, x, y, z) = \sum(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)$$

High State noise margin of standard TTL and 5V CMOSlogic gate are