If Sys clock frequency is > 4 * clk_ext frequency. What is the functionality of above circuit?

A

Falling Edgedetector with Pulse width of $$Q_{out} =$$ one cycle of Sys clk

B

Rising Edge detector with Pulse width of $$Q_{out} =$$ one cycle of Sys clk

C

Falling Edgedetector with Pulse width of $$Q_{out} =$$ one cycle of clk_ext

D

Rising Edge detector with Pulse width of $$Q_{out} =$$ one cycle of clk_ext