ISRO Scientist or Engineer Electronics 2018

Instructions

For the following questions answer them individually

ISRO Scientist or Engineer Electronics 2018 - Question 31


Consider identical four, 3-faced dice. When the dice are rolled, the faces of the dice appear with probabilities given below. Which distribution has the maximum entropy?

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ISRO Scientist or Engineer Electronics 2018 - Question 32


If System 1 and 2 are Linear Time Invariant systems and same input x(n) is provided both configuration
Statement 1: $$y_1(n) = y_2(n)$$
Statement 2: $$f(n) = g(n)$$

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ISRO Scientist or Engineer Electronics 2018 - Question 33


Benefit(s) of Bandpass sampling over low pass sampling

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ISRO Scientist or Engineer Electronics 2018 - Question 34


For a signal with $$F_c$$ (Centre Frequency) = 1200 MHz and BW = 100 MHz which of the following Sampling frequency($$F_s$$) will cause spectrum inversion:

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ISRO Scientist or Engineer Electronics 2018 - Question 35


If $$x_{in}(t) = \sin(2 * \pi * 4000 * t) + 0.75 * \sin \left(2 * \pi * 5000 * t + \frac{\pi}{4}\right)$$ is sampled with $$F_s = 16000 Hz$$ calculate $$X(0)$$ if $$X(m) = \sum_{n = 0}^{N - 1} x(n) e^{-j2 \pi nm/N}$$ When $$N = 8$$, where $$x(n) = x_{in}(nt_s)$$

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ISRO Scientist or Engineer Electronics 2018 - Question 36


VHDL
entity test is
port
(
data : in sd_logic;
clk : in std_logic;
reset : in std_logic;
q : out std_logic
);
end test;
architecture behav of test is
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '0') then
q $$\leq$$ '0';
else
q $$\leq$$ data;
end if;
end if;
end process;
end behav;
VERILOG
module test (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always @ (posedge clk)
if (~reset)
q = 1'b0;
else q = data;
endmodule
The Above Verilog/ VHDL module depicts which sequential element:

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ISRO Scientist or Engineer Electronics 2018 - Question 37


An ideal p-n junction diode in series with a 100 Ω resistance is forward biased such that the forward current flowing through the diode is 100 mA. If voltage across this circuit is instantaneously reversed to 20 V at time instant $$t = t_o$$, then the reverse current flowing through the diode at time instant $$t = t_o$$ is approximately given by

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ISRO Scientist or Engineer Electronics 2018 - Question 38


Determine output voltage ‘$$V_o$$’ for below circuit where $$V_{in} = \sin (100 \pi t)$$

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ISRO Scientist or Engineer Electronics 2018 - Question 39


Determine the channel half-width for an n-channel silicon FET having Gate-to-Source voltage, $$V_{GS} = \frac{V_p}{4}$$, where $$V_p$$ is the Pinch-off voltage and drain current, $$I_d = 0$$. (Consider (a) Donor Concentration $$N_D = 10^{15}$$ electrons/cm$$^3$$ (b) Channel half-width for $$V_{GS} = 0 V$$ is 3 $$\mu$$m).

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ISRO Scientist or Engineer Electronics 2018 - Question 40


Design a single section, quarter wave impedance transformer at 6 GHz from 4.75 cm $$\times$$ 2 cm guide to 3.75 cm $$\times$$ 1 em guide. Assume air filled wave guide with transformersection having same width as that of the input and output sections,

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cracku

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