VHDL
entity test is
port
(
data : in sd_logic;
clk : in std_logic;
reset : in std_logic;
q : out std_logic
);
end test;
architecture behav of test is
begin
process(clk)
begin
if (clk'event and clk = '1') then
if (reset = '0') then
q $$\leq$$ '0';
else
q $$\leq$$ data;
end if;
end if;
end process;
end behav;
VERILOG
module test (data, clk, reset, q);
input data, clk, reset;
output q;
reg q;
always @ (posedge clk)
if (~reset)
q = 1'b0;
else q = data;
endmodule
The Above Verilog/ VHDL module depicts which sequential element: