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For the following questions answer them individually
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)?
What is the minimum number of two-input NAND gates used to perform the function of two input OR gate?
If there are n devices (nodes) in a network, what is the number of cable links required for a fully connected mesh and a star topology respectively
