The output of the given logic circuit is:

Output of first NAND gate: $$G_1 = \overline{AB}$$

Output of second NAND gate (top): $$G_2 = \overline{A \cdot G_1} = \overline{A \cdot \overline{AB}} = \bar{A} + AB$$

Output of OR gate (bottom): $$G_3 = B + G_1 = B + \overline{AB} = B + \bar{A} + \bar{B} = 1$$

Final output of the last NAND gate: $$Y = \overline{G_2 \cdot G_3} = \overline{(\bar{A} + AB) \cdot 1} = \overline{\bar{A} + AB}$$

$$Y = \overline{\bar{A}} \cdot \overline{AB} = A \cdot (\bar{A} + \bar{B}) = A\bar{A} + A\bar{B} = 0 + A\bar{B} = A\bar{B}$$