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Question 20

Boolean relation at the output stage Y for the following circuit is:

Solution

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Boolean behavior of the parallel input diode network at the transistor base: $$V_b = A + B$$

Operation of the common-emitter transistor stage configured as an inverter: $$Y = \overline{V_b}$$

Combining the two stages: $$Y = \overline{A + B}$$

Applying De Morgan's laws: $$Y = \bar{A} \cdot \bar{B}$$

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