DMRC Electronics Engineering Paper-1 2016
For the following questions answer them individually
DMRC Electronics Engineering Paper-1 2016 - Question 61
The output of an exclusive-NOR gate is 1. Which input combination is correct?
DMRC Electronics Engineering Paper-1 2016 - Question 62
In figure v1 = 8 V and v2 = 4 V. Which diode will conduct?
DMRC Electronics Engineering Paper-1 2016 - Question 63
Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz:
DMRC Electronics Engineering Paper-1 2016 - Question 64
Initially the number decimal 8 is stored. If instruction RAL is executed twice, the final number stored will be:
DMRC Electronics Engineering Paper-1 2016 - Question 65
The output of an AND gate with three inputs, A, B, and C, is HIGH when ________:
DMRC Electronics Engineering Paper-1 2016 - Question 66
The gain of an FET amplifier can be changed by changing:
DMRC Electronics Engineering Paper-1 2016 - Question 67
In the case of a 70-MHz IF carrier for a transponder bandwidth of 36 MHz, energy must lie between MHz:
DMRC Electronics Engineering Paper-1 2016 - Question 68
In a full wave rectifier circuit using centre tapped transformer, the peak voltage across half of the secondary winding is 30 V. Then PIV is:
DMRC Electronics Engineering Paper-1 2016 - Question 69
The Lissajous pattern observed on screen of CRO is a straight line inclined at $$45^\circ$$ to x axis. If X-plate input is 2 sin ωt, the Y-plate input is
DMRC Electronics Engineering Paper-1 2016 - Question 70
The input impedance of op-amp circuit of figure is:
