The output from a NAND gate having inputs A and B given below will be,

Using NAND truth table condition: $$Y = \overline{A \cdot B}$$

Evaluating inputs interval by interval from the timing diagram:

Interval 1: $$A = 1, B = 1 \implies Y = \overline{1 \cdot 1} = 0$$

Interval 2: $$A = 0, B = 0 \implies Y = \overline{0 \cdot 0} = 1$$

Interval 3: $$A = 0, B = 1 \implies Y = \overline{0 \cdot 1} = 1$$

Interval 4: $$A = 1, B = 0 \implies Y = \overline{1 \cdot 0} = 1$$

Interval 5: $$A = 1, B = 1 \implies Y = \overline{1 \cdot 1} = 0$$

Interval 6: $$A = 0, B = 0 \implies Y = \overline{0 \cdot 0} = 1$$

Interval 7: $$A = 0, B = 1 \implies Y = \overline{0 \cdot 1} = 1$$