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Truth table for a standard 2-input NOR gate (Option A): $$\text{Outputs for } (0,0), (0,1), (1,0), (1,1) \implies 1, 0, 0, 0$$
Truth table for a standard 2-input OR gate (Option B): $$\text{Outputs for } (0,0), (0,1), (1,0), (1,1) \implies 0, 1, 1, 1$$
Truth table for a standard 2-input NAND gate (Option C): $$\text{Outputs for } (0,0), (0,1), (1,0), (1,1) \implies 1, 1, 1, 0$$
Analysis of Option D (NOR gate with shorted inputs acting as a NOT gate): $$\text{Output for } A = 0 \implies Y = 1$$
$$\text{Output for } A = 1 \implies Y = 0$$
Since each distinct output uniquely determines a single unique input, the mapping is one-to-one (reversible).
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