Consider two npn transistors as shown in the figure. If 0 Volts corresponds to false and 5 Volts correspond to true, then the output at C corresponds to :

An npn transistor acts as a closed switch when its base is high ($$5\text{ V}$$) and an open switch when its base is low ($$0\text{ V}$$). Because the transistors are in series, both must be ON simultaneously to create a path to ground.

If either $$A$$ or $$B$$ (or both) are $$0\text{ V}$$, at least one transistor remains OFF. No current flows to ground, and the output $$C$$ is pulled up to $$5\text{ V}$$ (Logic $$1$$).

If both $$A$$ and $$B$$ are $$5\text{ V}$$, both transistors are ON. The output $$C$$ is shorted to ground, resulting in $$0\text{ V}$$ (Logic $$0$$).

This logic corresponds to a NAND gate.