In VHDL following statement 18 written within a Process, where Clock frequency is 24 MHZ
If (Clock event and clock = ‘1’) then
counter_4 bit < = counter_4 bit + x "1" ;
End if;
The frequency of counter_4 bit (2) will be:

A

12 MHZ

B

4 MHZ

C

6 MHZ

D

3 MHZ