Consider the following assembly code for a hypothetical RISC processor with a 4-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).
add $$r_{1},r_{2},r_{3} \parallel r_{1} = r_{2} + r_{3}$$
sub $$r_{4},r_{1},r_{3} \parallel r_{4} = r_{1} - r_{3}$$
mul $$r_{5},r_{2},r_{3} \parallel r_{5} = r_{2} \star r_{3}$$
Identify the possible pipeline hazard and the affected instruction.